The present invention relates to a special class of integrated circuit dynamic random access memories (DRAMs) More particularly, the invention involves random access memories configured with elements which perform logical operations on the data stored within the RAM during a single access cycle, in contrast to a conventional read-modify-write succession of cycles.
Dynamic random access memories and their applications are well known by those even moderately skilled in digital computer technology. As conventionally used, memory arrays are arranged to store binary data which is written to individual cells by selecting the row and column addresses thereof from within the array. Extraction of previously stored data is completed through a similarly addressed read operation, which operation concurrently refreshes the data in the selected cell. If the data stored in the cell of the memory array is to be logically combined with external data and thereafter again stored within the same cell, the conventional practice has been to execute a read-modify-write sequence of operations. In a conventional clock synchronized system such logical combination routine extends over at least one and one-half memory array access time intervals and thus tends to be one of the slowest of processor operations.
The application of random access memories in frame buffers of the video displays, and the concurrent increase in the pixel count and color variations expected of contemporary video displays, has led to an accentuated need for increasing the rate at which binary data from a dynamic random memory array cell can be logically combined with new data and then returned to the same frame buffer cell address. Therefore, there exists a present need for computer architecture and circuitry which allows logical combinations of memory array cell data with external data within the memory array structure, in contrast to transferring the previously stored memory data to a processor ALU, performing the logical operations, and thereafter returning the resultant data to the same memory cell.
Various teachings in the references relate to this problem. For instance, the U.S. Pat. No. 4,016,544 uses mask initiated writing of bits into memory, but provides no logical combination with previous data in memory. The apparatus in U.S. Pat. No. 3,787,817 uses closely coupled logic to combine previously stored data with new data, but does so in the classic read-modify-write operational sequence. A somewhat more refined use of combinational logic is described in the article entitled "Video DRAMs Shift Image of Graphics Systems" by Wilson, as appeared in the April 1986 issue Digital Design. However, again the combinational logic is drawn into use in the context of a conventional read-modify-write sequence of memory operation. Integration of logic and memory array functions is disclosed in U.S. Pat. No. 4,586,169. In this case, however, each memory cell in the array is arranged to include logic capability. Unfortunately, the latter implementation results in a memory array of inordinate size and cost for the benefits obtained.
Accordingly, there remains the need for an efficient architecture and circuitry by which memory array cell data can be extracted, logically combined with new data, and returned to the memory array cell in less time than the conventional read-modify-write sequence entails. Furthermore, the logical combinations of previously stored data and new data should be sufficiently diverse to permit routine use in high speed and high definition video display applications.